This picture is right out of the BlackFin HRM.
Without repeating what is already covered in the HRM let us try to analyse the capabilities of the Core from a different perspective.
Load Store Architecture means
- All the operations are done on the registers
- That would in turn mean that all the computational units in the core needs their inputs from the registers
- This mandates that there has to be internal buses which connect the computational units to the registers.
- A set of buses as the input and another set which transmits the output back to the registers.
The Diagram Below depicts exactly what we need.
This is quite fascinating, we can exactly know the reason why some instructions work while others do not.
Consider the Operation :
R0 = R1+ R2;
How does this work? There are two 32 bit buses running from the Data register file to the ALU0, values inside R1 & R2 will be transferred through them into ALU0 and once the operation is done the data come out back and gets written into R0. Perfect!
Now why does the following operation does not work?
P0 = R0 + R1;
The answer lies again in the bus architecture. Eventhough R0 and R1 can be transferred to ALU0 we do not have a Bus running from ALU0 to Pointer Register File, hence there is no way that this operation can succeed.
*Please note that by default ALU0 will be used and ALU 1 will come into picture only in case of parallel operations, which can be discussed in another post.
Idea here is to prod us to start thinking from this perspective. When we understand the bus architecture, we understand how to write the best possible assembly code while remaining within the constraints of the system. All this data and instruction buses connecting memory, registers & computational units form the backbone of an architecture. This inherently determines the strengths as well as the weakness of the processor.